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| products and specifications discussed herein ar e subject to change by micron without notice. 2gb, 4gb, 8gb: x8, x16 nand flash memory features pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__1.fm - rev. d 12/06 en 1 ?2005 micron technology, inc. all rights reserved. nand flash memory mt29f2g08aacwp, mt29f4g08bacwp, mt29f8g08facwp for the latest data sheet, refer to the micron web site: www.micron.com/products/nand / features ? organization ? page size x8: 2,112 bytes (2,048 + 64 bytes) ? page size x16: 1,056 words (1,024 + 32 words) ? block size: 64 pages (128k + 4k bytes) ? device size: 2gb: 2,048 bl ocks; 4gb: 4,096 blocks; 8gb: 8,192 blocks read performance ? random read: 25s ? sequential read: 30ns (3v x8 only) write performance ? program page: 300s (typ) ? block erase: 2ms (typ) endurance: 100,000 program/erase cycles first block (block address 00h) guaranteed to be valid without ecc (up to 1,000 program/erase cycles) v cc : 1.70v?1.95v 1 or 2.7v?3.6v automated program and erase basic nand flash command set: ? page read, read for internal data move, random data read, read id, read status, program page, random data input, pro- gram page cache mode, program for internal data move, block erase, reset new commands: ? page read cache mode ? one-time programmable (otp), including: otp data program, otp data protect, otp data read ? read unique id (contact factory) ? read id2 (contact factory) operation status byte provides a software method of detecting: ? program/erase oper ation completion ? program/erase pass/fail condition ? write-protect status ready/busy (r/b#) pin provides a hardware method of detecting program or erase cycle completion wp# pin: hardware write protect figure 1: 48-pin tsop type 1 options marking density: ? 2gb (single die) mt29f2g ? 4gb (dual-die stack) mt29f4g ? 8gb (quad-die stack) mt29f8g device width: ? x8 mt29fxx08x ? x16 1 mt29fxx16x configuration: # of die # of ce# # of r/b# 11 1 a 21 1 b 42 2 f v cc : ? 2.7v?3.6v a ? 1.70v?1.95v 1 b third-generation die c package: ? 48-pin tsop type i (lead-free) wp operating temperature: ? commercial (0c to 70c) none ? extended (?40c to +85c) 2 et notes: 1. packaged parts are only available for 3v x8 devices. for 1.8v or x16 devices, contact factory. 2. for et devices, contact factory.
pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__1.fm - rev. d 12/06 en 2 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory part numbering information part numbering information micron ? nand flash devices are available in several different configurations and densities (see figure 2). figure 2: part number chart valid part number combinations after building the part number from the part numbering chart above, verify that the part number is valid using the micron parametric part search at www.micron.com/products/ parametric . if the device required is not on this list, contact the factory. mt 29f 2g 08 a a c wp es :c micron technology product family 29f = single-supply nand flash memory density 2g = 2gb 4g = 4gb 8g = 8gb device width 08 = 8 bits 16 = 16 bits operating voltage range a = 3.3v (2.70v?3.60v) b = 1.8v (1.70v?1.95v) design revision c = first generation production status blank = production es = engineering sample ms = mechanical sample qs = qualification sample operating temperature range blank = commercial (0c to +70c) et = extended (?40c to +85c) reserved for future use flash performance blank = standard package codes wp = 48-pin tsop i (lead-free) feature set a = first-generation die b = second-generation die c = third-generation die classification # of die # of ce# # of r/b# i/o a 1 1 1 common b 2 1 1 common f 4 1 1 common pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49atoc.fm - rev. d 12/06 en 3 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pin assignments and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 ready/busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 page read 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 random data read 05h-e0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 page read cache mode start 31h; page read cache mo de start last 3fh . . . . . . . . . . . . . . . . .22 read id 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 read status 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 program page 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 serial data input 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 random data input 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 program page cache mode 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 read for internal data move 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 program for internal data move 85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 block erase 60h-d0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 one-time programmable (otp) area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 otp data program a0h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 otp data protect a5h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 otp data read afh-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 reset ffh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 write protect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 v cc power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49alof.fm - rev. d 12/06 en 4 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory list of figures list of figures figure 1: 48-pin tsop type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3: nand flash functional block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4: 48-pin tsop type 1 pin assignments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5: memory map x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6: memory map x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7: array organization for mt29f2g08axc (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8: array organization for mt29f2g16axc (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9: array organization for mt29f4g 08bxc and mt29f8g08fxc (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10: array organization for mt28f4g16bxc and mt29f8g16f xc (x16) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11: ready/busy# open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12: tfall and trise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13: iol vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16: page read cache mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 18: status register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 19: program and read status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 20: random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 21: program page cache mo de example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 22: internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 23: internal data move with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 24: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 25: otp data program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 26: otp data protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 27: otp data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 28: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 29: erase enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 30: erase disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 31: program enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 32: program disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 33: ac waveforms during power transi tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 34: command latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 35: address latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 36: input data latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 37: serial access cycle after read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 38: read status cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 39: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 40: page read operation with ce# ?d on?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 41: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 42: page read cache mode operation, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 43: page read cache mode operation, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 44: page read cache mode operation without r/b#, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 45: page read cache mode operation without r/b#, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 46: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 47: program page operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 48: program page op eration with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 49: program page operation with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 50: internal data move operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 51: program page cache mode operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 52: program page cache mode operat ion ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 53: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 54: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 55: tsop type i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49alot.fm - rev. d 12/06 en 5 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory list of tables list of tables table 1: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2: operational example (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3: operational example (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4: array addressing: mt29f2g08axc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5: array addressing: mt29f2g16axc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6: array addressing for mt29f4g08bxc and mt29f8g08fxc (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7: array addressing for mt28f4g16bxc and mt29f8g16fxc (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9: command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10: device id and configuration codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11: status register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12: status register contents after re set operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13: absolute maximum ratings by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 14: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 15: m29fxgxxxac 3v device dc and operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16: m29fxgxxxbc 1.8v device dc and operating characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17: valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 19: test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20: ac characteristics: command, data, and address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 21: ac characteristics: normal operat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 22: program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 6 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory general description general description nand flash technology provides a cost-effec tive solution for applications requiring high-density, solid-state storage. micron mt29f2g08axc and mt29f2g16axc devices are 2gb nand flash memory devices. the mt29f4g08bxc and mt29f4g16bxc are 4gb devices. the mt29f8g08fac is a four-die stack that operates as two independent 4gb devices, providing a total storage capacity of 8gb in a single, space-saving package. these devices include standard nand flash feat ures as well as new features designed to enhance system-level performance. micron nand flash devices use a highly mu ltiplexed 8- or 16-b it bus (i/o[7:0] or i/o[15:0]) to transfer data, addresses, and instructions. the five command pins (cle, ale, ce#, re#, we#) implement the nand fl ash command bus interface protocol. two additional pins control hardware write pr otection (wp#) and mo nitor device status (r/b#). this hardware interface creates a low-pin-coun t device with a standard pinout that is the same from one density to another, suppor ting future upgrades to higher densities without board redesign. the mt29f2g and mt29f4g devices contain 2,048 and 4,096 erasable blocks, respec- tively. each block is subdivided into 64 programmable pages. each page consists of 2,112 bytes (x8) or 1,056 words (x16). the page s are further divided into a 2,048-byte data storage region with a separate 64-byte area on the x8 device; and on the x16 device, sep- arate 1,024-word and 32-word areas. the 64-byte and 32-word areas are typically used for error management functions. the contents of each 2,112-byte page can be programmed in 300s, and an entire 132k- byte/66k-word block can be erased in 2ms. on-chip control logic automates program and erase operations to maximize cycle endurance. erase/program endurance is specified at 100,000 cycles when appropriat e error correction code (ecc) and error management are used. figure 3: nand flash functional block diagram address register data register cache register status register command register ce# v cc v ss cle ale we# re# wp# i/o [7:0] i/o [15:0] control logic i/o control r/b# row decode column decode pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 7 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory pin assignments and descriptions pin assignments and descriptions figure 4: 48-pin tsop type 1 pin assignments (top view) notes: 1. r/b2# and ce2# are avai lable only on 8gb devices. these pins are nc for other configurations. x8 nc nc nc nc nc r/b2# 1 r/b# re# ce# ce2# 1 nc v cc v ss nc nc cle ale we# wp# dnu dnu dnu nc nc x16 nc nc nc nc nc r/b2# 1 r/b# re# ce# ce2# 1 nc v cc v ss nc nc cle ale we# wp# dnu dnu dnu nc nc x16 v ss i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 nc dnu or v ss v cc nc nc nc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 v ss x8 nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc dnu or v ss v cc v ss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 8 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory pin assignments and descriptions table 1: pin descriptions symbol type description ale input address latch enable: duri ng the time ale is high, address information is transferred from i/o[7:0] into the on-c hip address register upon a low-to-high transition on we# . when address information is not being loaded, the ale pin should be driven low. ce#, ce2# input chip enable: this gates transfers betw een the host system and the nand flash device. once the device starts a program or erase operation, the chip enable pin can be de-asserted. for the 8gb configuration, ce# controls the first 4gb of memory; ce2# controls the second 4gb. see ?bus operation? on page 16 for additional operational details. in the 8gb configuration, r/b# is for the 4gb of memory enabled by ce#; r/b2# is for the 4gb of memory enabled by the ce2#. cle input command latch enable: when cle is hi gh, information is transferred from i/o[7:0] to the on-chip co mmand register on the rising edge of we#. when command information is not being loaded, cle should be driven low. re# input read enable: this gates transfers from the nand flash device to the host system. we# input write enable: this gates transfers from the host system to the nand flash device. wp# input write protect: pin protects against inad vertent program and erase operations. all program and erase operations are disabled when the wp# pin is low. i/o[7:0] mt29fxg08 i/o[15:0] mt29fxg16 i/o data inputs/outputs: the bidirectional i/o pins transfer address, data, and instruction information. data is output only during read operations; at other times the i/o pins are inputs. r/b#, r/b2# output ready/busy: an open-drain, active-low ou tput that uses an external pull-up resistor, the pin is used to indicate when the chip is processing a program or erase operation. the pin is also used du ring a read operation to indicate when data is being transferred from the array in to the serial data register. when these operations have completed, the r/ b# returns to the high-z state. v cc supply v cc : power supply. v ss supply v ss : ground connection. nc ? no connect: nc pins are not internally connected. these pins can be driven or left unconnected. dnu ? do not use: these pins must be left unconnected. pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 9 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory architecture architecture these devices use nand flash electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins to provide a memory device with a low pin count. the internal memory array is accessed on a pa ge basis. during reads, a page of data is copied from the memory array into the data register. once copied to the data register, data is output sequentially, byte by byte on x8 devices, or word by word on x16 devices. the memory array is programmed on a page basis. after the starting address is loaded into the internal address register, data is sequ entially written to the internal data register up to the end of a page. after all of the page data has been loaded into the data register, array programming is started. in order to increase programming bandwidth, this device incorporates a cache register. in the cache programming mode, data is first copied into the cache register and then into the data register. when the data is copied into the data register, programming begins. after the data register has been loaded and programming has started, the cache register becomes available for loading of additional da ta. loading of the next page of data into the cache register takes place whil e page programming is in process. the internal data move command also uses the internal cache register. normally, moving data from one area of external memo ry to another uses a large number of exter- nal memory cycles. with the use of the internal cache register and data register, array data can be copied from one page and then programmed into another without the use of external memory cycles. addressing nand flash devices do not contain dedicate d address pins. addresses are loaded using a five-cycle sequence, as shown in tables 4 and 5 on pages 12 and 13. see figures 5 and 6 on pages 10 and 11 for additional memory mapping and addressing details. pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 10 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory memory mapping memory mapping figure 5: memory map x8 notes: 1. as shown in table 4 on page 12, the high nibble of address cycle 2 has no assigned address bits; however, these 4 bits must be held low during the address cycle to ensure that the address is interpreted correctly by the nand flash device. these extr a bits are accounted for in address cycle 2 even though they do not have address bits assigned to them. 2. the 12-bit column address is capable of addres sing from 0 to 4,095 bytes on x8 devices; however, only bytes 0 through 2,111 are valid. bytes 2,112 through 4,095 of each page are ?out of bounds,? do not exist in the device, and cannot be addressed. table 2: operational example (x8) block page min address in page max address in page out-of-bounds addresses in page 0 0 0x0000000000 0x000000083f 0x0000000840?0x0000000fff 0 1 0x0000010000 0x000001083f 0x0000010840?0x0000010fff 0 2 0x0000020000 0x000002083f 0x0000020840?0x0000020fff ?? ? ? 2,046 62 0x01fffe0000 0x01fffe083f 0x01fffe0840?0x01fffe0fff 2,047 63 0x01ffff0000 0x01ffff0 83f 0x01ffff0840?0x01ffff0fff blocks ba[16:6] pages pa[5:0] bytes ca[11:0] 012 012 63 0 1 2 2,047 2,111 2,047 spare area pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 11 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory memory mapping figure 6: memory map x16 notes: 1. as shown in table 5 on page 13, the uppe r 5 bits of address cycle 2 have no assigned address bits; however, these 5 bits must be held low during the addr ess cycle to ensure that the address is interpreted correctly by the nand flash device. these extra bits are accounted for in address cycle 2 even though they do not ha ve address bits assigned to them. 2. the 11-bit column address is capable of addres sing from 0 to 2,047 words on x16 devices; however, only words 0 throug h 1,055 are valid. words 1,056 through 2,048 of each page are ?out of bounds,? do not exist in the device, and cannot be addressed. table 3: operational example (x16) block page min address in page max address in page out-of-bounds addresses in page 0 0 0x0000000000 0x000000041f 0x0000000420?0x0000000fff 0 1 0x0000010000 0x000001041f 0x0000010420?0x0000010fff 0 2 0x0000020000 0x000002041f 0x0000020420?0x0000020fff ?? ? ? 2,046 62 0x01fffe0000 0x01fffe041f 0x01fffe0420?0x01fffe0fff 2,047 63 0x01ffff0000 0x01ffff0 41f 0x01ffff0420?0x01ffff0fff blocks ba[16:6] pages pa[5:0] words ca[10:0] 012 012 63 0 1 2 1,023 1,055 2,047 spare area pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 12 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory memory mapping figure 7: array organization for mt29f2g08axc (x8) notes: 1. if ca11 = ?1? then ca[10:6] must be ?0.? 2. block address concatenated with page address = actual page address; cax = column address; pax = page address; bax = block address. table 4: array addressing: mt29f2g08axc cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second lowlowlowlowca11 1 ca10 ca9 ca8 third ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low low ba16 cache register data register 2,048 blocks per device 1 block 64 2,048 64 2,048 2,112 bytes i/o 7 i/o 0 64 pages = 1 block (128k + 4k) bytes 1 page = (2k + 64) bytes 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 device = (2k + 64) bytes x 64 pages x 2,048 blocks = 2,112mb pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 13 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory memory mapping figure 8: array organization for mt29f2g16axc (x16) note: for x16 devices, contact factory. notes: 1. if ca10 = ?1? then ca[9:5] must be ?0.? 2. block address concatenated with page address = actual page address. cax = column address; pax = page address, bax = block address. 3. i/o[15:8] are not used during the addre ssing sequence and should be driven low. table 5: array addressing: mt29f2g16axc cycle i/o[15:8] i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first low ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low low low ca10 1 ca9 ca8 third low ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth low ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low lo wlowlowlowba16 cache register data register 2,048 blocks per device 1 block 32 1,024 32 1,024 1,056 words i/o 15 i/o 0 64 pages = 1 block (64k + 2k) words 1 page = (1k + 32) words 1 block = (1k + 32) words x 64 pages = (64k + 2k) words 1 device = (1k + 32) words x 64 pages x 2,048 blocks = 2,112mb pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 14 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory memory mapping figure 9: array organization for mt29f4g08bxc and mt29f8g08fxc (x8) note: for the 8gb mt29f8g08f, the 4gb array or ganization shown applies to each chip enable (ce# and ce2#). notes: 1. if ca11 = ?1? then ca[10:6] must be ?0.? 2. die address boundary: ?0? = 0gb?2g b devices; ?1? = 2gb?4gb devices. 3. block address concatenated with page address = actual page address. cax = column address; pax = page address; bax = block address. table 6: array addressing for mt29f4g08bxc and mt29f8g08fxc (x8) cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second lowlowlowlowca11 1 ca10 ca9 ca8 third ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low ba17 2 ba16 cache register data register 4,096 blocks per device 1 block 64 2,048 64 2,048 2,112 bytes i/o 7 i/o 0 64 pages = 1 block (128k + 4k) bytes 1 page = (2k + 64) bytes 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 device = (2k + 64) bytes x 64 pages x 4,096 blocks = 4,224mb pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 15 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory memory mapping figure 10: array organization for mt28f4g16bxc and mt29f8g16fxc (x16) notes: 1. for x16 device s, contact factory. 2. for the 8gb mt29f8g16f, the 4gb array orga nization shown applies to each chip enable (ce# and ce2#). notes: 1. if ca10 = ?1? then ca[9:5] must be ?0.? 2. die address boundary: ?0? = 0gb?2g b devices, ?1? = 2gb?4gb devices. 3. block address concatenated with page address = actual page address. cax = column address; pax = page address; bax = block address. 4. i/o[15:8] are not used during the addre ssing sequence and should be driven low. table 7: array addressing for mt28f4g16bxc and mt29f8g16fxc (x16) cycle i/o[15:8] i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first low ca7ca6ca5ca4ca3ca2ca1ca0 second low low low low low low ca10 1 ca9 ca8 third low ba7 ba6 pa5 pa4 pa3 pa2 pa1 pa0 fourth low ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low low ba17 2 ba16 cache register data register 4,096 blocks per device 1 block 32 1,024 32 1,024 1,056 words i/o 15 i/o 0 64 pages = 1 block (64k + 2k) words 1 page = (1k + 32) words 1 block = (1k + 32) words x 64 pages = (64k + 2k) words 1 device = (1k + 32) words x 64 pages x 4,096 blocks = 4,224mb pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 16 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory bus operation bus operation the bus on the mt29fxxx devices is multip lexed. data i/o, addresses, and commands all share the same pins. i/o pins i/o[15:8] ar e used only for data in the x16 configura- tion. addresses and commands are always supplied on i/o[7:0]. the command sequence normally consists of a command latch cycle, an address latch cycle, and a data cycle?either read or write. control signals ce#, we#, re#, cle, ale and wp# control nand flash device read and write opera- tions. on the 8gb mt29f8g08fac, ce# and ce2# each control independent 4gb arrays. ce2# functions the same as ce# for its own ar ray; all operations described for ce# also apply to ce2#. ce# is used to enable the device. when ce# is low and the device is not in the busy state, the nand flash memory will acce pt command, data, and address information. when the device is not performing an operat ion, ce# is typically driven high and the device enters standby mode. the memory will enter standby if ce# goes high while data is being transferred and the device is not busy. this helps reduce power consump- tion. see figure 40 on page 47 and figure 48 on page 53 for examples of ce# ?don?t care? operations. the ce# ?don?t care? operation enables the nand flash to reside on the same asyn- chronous memory bus as other flash or sram devices. other devices on the memory bus can then be accessed while the nand flas h is busy with internal operations. this capability is important for designs that re quire multiple nand flash devices on the same bus. one device can be programmed while another is being read. a high cle signal indicates th at a command cycle is taking place. a high ale signal signifies that an address input cycle is occurring. commands commands are written to the command register on the rising edge of we# when: ce# and ale are low, and cle is high, and the device is not busy. the exceptions to this are the read status and reset commands when busy. see figure 34 on page 44 for detailed timing requirements. commands are input on i/o[7:0] only. for devices with a x16 interface, i/o[15:8] must be written with zeros when a command is issued. address input addresses are written to the address register on the rising edge of we# when: ce# and cle are low, and ale is high, and the device is not busy. addresses are input on i/o[7:0] only; bits not part of the address space must be low. for devices with a x16 interface, i/o[15:8] must be written with zeros when an address is issued. the number of address cycles required for each command varies. refer to the com- mand descriptions to determine addressing requirements (see table 9 on page 20). pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 17 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory bus operation data input data is written to the data register on the rising edge of we# when: ce#, cle, and ale are low, and the device is not busy. data is input on i/o[7:0] for x8 devices, an d on i/o[15:0] for x16 devices. see figure 36 on page 45 for additional data input details. reads after a read command is issued, data is tran sferred from the memory array to the data register on the rising edge of we#. r/b# goes low for t r and transitions high after the transfer is complete. when r/b# goes high, data is available in the data register; it is clocked out of the part by toggling re#. see figure 39 on page 46 for detailed timing information. the read status (70h) command or the r/b# signal can be used to determine when the device is ready. see the read status command section on page 26 for details. ready/busy# the r/b# output provides a hardware meth od of indicating th e completion of pro- gram, erase, and read operations. the signal requires a pull-up resistor for proper operation. the signal is typically high, an d transitions to low after the appropriate command is written to the device. the signal pin?s open-drain driver enables multiple r/b# outputs to be or-tied. the read status command can be used in place of r/b#. typically, r/b# is connected to an interrupt pin on the system controller (see figure 11 on page 18 ). on the 8gb mt29f8g08fac, r/b# provides a status indication for the 4gb section enabled by ce#, and r/b2# does the same fo r the 4gb section enabled by ce2#. r/b# and r/b2# can be tied together, or they can be used separately to provide independent indications for each 4gb section. the combination of rp and capacitive loadin g of the r/b# circuit determines the rise time of the r/b# pin. the actual value used for rp depends on the system timing requirements. large values of rp cause r/b# to be delayed significantly. at the 10 per- cent to 90 percent points on the r/b# wave form, rise time is approximately two time constants (tc). the fall time of the r/b# signal is determ ined mainly by the output impedance of the r/b# pin and the total load capacitance. figure 12 on page 18 and figure 13 on page 19 depict approximate rp values using a cir- cuit load of 100pf. the minimum value for rp is determined by th e output drive capability of the r/b# sig- nal, the output voltage swing, and v cc . tc r c = where r = rp (resistance of pull-up resi stor), and c = total capacitive load. rp min () v cc max () v ol max () ? i ol il + --------------------------------------------------------------- 1.85 v 3 ma il + -------------------------- == where i l is the sum of the input currents of all devices tied to the r/b# pin. pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 18 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory bus operation figure 11: ready/busy# open drain figure 12: t fall and t rise notes: 1. t fall and t rise are calculated at 10 percent and 90 percent points. 2. t rise is primarily dependent on external pull -up resistor and extern al capacitive loading. 3. t fall 10ns at 3.3v; t fall 7ns at 1.8v. rp r/b# open drain output v cc gnd device i ol 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 6 t fall t rise vcc 3.3 vcc 1.8 tc v pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 19 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory bus operation figure 13: i ol vs. rp notes: 1. wp# should be biased to cmos high or low for standby. 2. h = logic level high; l = logic level low; x = v ih or v il . table 8: mode selection cle ale ce# we# re# wp# 1 mode hl l hx read mode command input lh l hx address input hl l hh write mode command input lh l hh address input ll l hh data input ll lh x sequential read and data output ll lhhx during read (busy) xx x x xh during program (busy) xx x x xh during erase (busy) xx x x xl write protect xx h x x0v/v cc standby 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0 2,000 4,000 6,000 8,000 10,000 12,000 rp ( ? ) t (s) i ol at 3.60v (ma) i ol at 1.95v (ma) pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 20 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions command definitions notes: 1. indicates required data cycles be tween command cycle 1 and command cycle 2. 2. do not cross die boundaries when using read for internal data move and program for internal data move. 3. random data read command is limited to use within a single page. 4. random data input command is limi ted to use within a single page. table 9: command set operation command cycle 1 number of address cycles data cycles required 1 command cycle 2 valid during busy notes page read 00h 5 no 30h no page read cache mode start 31h ? no ? no page read cache mode start last 3fh ? no ? no read for internal data move 00h 5 no 35h no 2 random data read 05h 2 no e0h no 3 read id 90h 1 no ? no read status 70h ? no ? yes program page 80h 5 yes 10h no program page cache mode 80h 5 yes 15h no program for internal data move 85h 5 optional 10h no 2 random data input 85h 2 yes ? no 4 block erase 60h 3 no d0h no reset ffh ? no ? yes otp data program a0h 5 yes 10h no otp data protect a5h 5 no 10h no otp data read afh 5 no 30h no pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 21 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions read operations page read 00h-30h on initial power-up, the device defaults to read mode. to enter the read mode while in operation, write the 00h command to the co mmand register, then write five address cycles followed by the 30h command. to determine the progress of the data transfer from the nand flash array to the data register ( t r), monitor the r/b# signal, or, alternat ively, issue a read status (70h) com- mand. if the read status command is used to monitor the data transfer, the user must re-issue the read (00h) command to receive data output from the data register. see figure 44 on page 50 and figure 45 on page 51 for examples. after the read com- mand has been re-issued, pulsing the re# line will result in outp utting data, starting from the initial column address. a serial page read sequence outputs a complete page of data. after 30h is written, the page data is transferred to the data regist er, and r/b# goes low during the transfer. when the transfer to the data register is complete, r/b# returns high. at this point, data can be read from the device. starting from the initial column address and going to the end of the page, read the data by repeatedly pulsing re# at the maximum t rc rate (see figure 14). figure 14: page read operation d out n d out n + 1 d out m we# ce# ale cle re# r/b# i/ox t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz don?t care col add 1 col add 2 row add 1 row add 2 row add 3 pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 22 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions random data read 05h-e0h the random data read command enables the user to specify a new column address so the data at single or multiple addresses can be read. the random read mode is enabled after a normal page read (00h-30h) sequence. random data can be output after the initial page read by writing an 05h-e0h command sequence along with the new column address (two cycles). the random data read command can be issued without limit within the page. only data on the current page can be read. pulsing the re# pin outputs data sequentially (see figure 15). figure 15: random data read operation page read cache mode start 31h; page read cache mode start last 3fh micron nand flash devices have a cache register that can be used to increase the read operation speed when accessing sequential pages in a block. first, a normal page read (00h-30h) comma nd sequence is issued. see figure 16 on page 23 for operation details. the r/b# signal goes low for t r during the time it takes to transfer the first page of data from the memory to the data register. after r/b# returns to high, the page read cache mode start (31h) command is latched into the com- mand register. r/b# goes low for t dcbsyr1 while data is being transferred from the data register to the cache register. when the data register contents are transferred to the cache register, another page read is automa tically started as part of the 31h command. data is transferred from the next sequential page of the memory array to the data regis- ter during the same time data is being read serially (pulsing of re#) from the cache regis- ter. if the total time to output data exceeds t r, then the page read is hidden. the second and subsequent pages of data are transferred to the cache register by issuing additional 31h commands. r/b# will stay low up to t dcbsyr2. this time can vary, depending on whether the previous memory -to-data-register transfer was completed prior to issuance of the next 31h command. see table 21 on page 43 for timing parame- ters. if the data transfer from memory to the data register is not completed before the 31h command is issued, r/b# stays low until the transfer is complete. it is not necessary to output a whole page of data before issuing another 31h command. r/b# will stay low until the previous page read is complete and the data has been transferred to the cache register. to read out the last page of data, the page read cache mode start last (3fh) command is issued. this command transfers da ta from the data register to the cache register without issuing another page read (see figure 16 on page 23 ). re# i/ox 00h address (5 cycles) data output data output 30h 05h address (2 cycles) e0h r/b# t r pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 23 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions figure 16: page read cache mode re# ce# ale cle i/ox 00h address (5 cycles) 31h 30h 31h 3fh r/b# we# t r t dcbsyr1 t dcbsyr2 t dcbsyr2 don?t care data output (serial access) data output (serial access) data output (serial access) pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 24 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions read id 90h the read id (90h) command is used to read the 4 bytes of identifier codes programmed into the devices. the read id command re ads a 4-byte table th at includes manufac- turer id, device configuration, and part-spe cific information (see table 10 on page 25). writing 90h to the command register puts the device into the read id mode. the com- mand register stays in this mode until the next command cycle is issued (see figure 17 ). figure 17: read id operation notes: 1. see table 10 on pa ge 25 for byte definitions. we# ce# ale cle re# i/ox address, 1 ccycle 90h 00h byte 2 byte 0 byte 1 byte 3 t ar t rea t whr pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 25 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions notes: 1. b = binary; h = hex. 2. device ids for these configurations are provided for reference only. 3. the mt29f8g08fac device id code reflec ts the configuration of each 4gb section. table 10: device id and configuration codes options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value 1 notes byte 0 manufacturer id micron 001011002ch byte 1 device id mt29f2g08aac 2gb, x8, 3v 1 1 0 1 1 0 1 0 dah mt29f2g08abc 2gb, x8, 1.8v 1 0 1 0 1 0 1 0 aah 2 mt29f2g16aac 2gb, x16, 3v 1 1 0 0 1 0 1 0 cah 2 mt29f2g16abc 2gb, x16, 1.8v 1 0 1 1 1 0 1 0 bah 2 mt29f4g08bac 4gb, x8, 3v 1 1 0 1 1 1 0 0 dch mt29f8g08fac 8gb, x8, 3v 1 1 0 1 1 1 0 0 dch 3 byte 2 byte value don?t care xxxxxxxxxxh byte 3 page size 2kb 0 1 01b spare area size (bytes) 64 0 1 01b block size (w/o spare) 128kb 0 1 01b organization x8 00b x16 11b reserved 00b byte value x8 0001010115h x16 0101010155h pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 26 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions read status 70h nand flash devices have an 8- bit status register that th e software can read during device operation. on the x16 device, i/o[15:8] are ?0? when the status register is being read. table 11 describes the status register. after a read status command, all read cycles will be from the status register until a new command is issued. changes in the status register will be seen on i/o[7:0] as long as ce# and re# are low; it is not necessary to start a new read status cycle to see these changes. while monitoring the read status to determine when the t r (transfer from nand flash array to data register) is complete, the user must re-issue the read (00h) command to make the change from status mode to read mode. after the read command has been re-issued, pulsing the re# line will result in outputting data, starting from the initial col- umn address. notes: 1. status register bit 5 is ?0? during the actual programming operation. if cache mode is used, this bit will be ?1? when al l internal operatio ns are complete. 2. status register bit 6 is ?1? wh en the cache is ready to accept new data. r/b# follows bit 6. see figure 16 on page 23 and figure 21 on page 28. figure 18: status register operation table 11: status register bit definition sr bit program page program page cache mode page read page read cache mode block erase definition 0 pass/fail pass/fail (n) ? ? pass/fail ?0? = successful program/erase ?1? = error in program/erase 1 ? pass/fail (n-1) ? ? ? ?0? = successful program/erase ?1? = error in program/erase 2? ? ? ? ? ?0? 3? ? ? ? ? ?0? 4? ? ? ? ? ?0? 5 ready/busy ready/busy 1 ready/busy ready/busy 1 ready/busy ?0? = busy ?1? = ready 6 ready/busy ready/busy cache 2 ready/busy ready/busy cache 2 ready/busy ?0? = busy ?1? = ready 7 write protect write protect write protect write protect write protect ?0? = protected ?1? = not protected [15:8] ? ? ? ? ? ?0? 70h ce# cle we# re# i/ox status output t rea t clr pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 27 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions program operations program page 80h-10h micron nand flash devices are inherently page-programmed devices. pages must be programmed consecutively within a block, fr om the least significant page address to the most significant page address (i.e., 0, 1, 2, ?, 63). random page address programming is prohibited. micron nand flash devices also support partial-page programming operations. this means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned such that a maximum of eight programming oper- ations are allowed before an erase is required. serial data input 80h program page operations require loading of the serial data input (80h) com- mand into the command register, followed by five address cycles, then the data. serial data is loaded on consecutive we# cycles, starting at the given address. the program (10h) command is written after the data inpu t is complete. the co ntrol logic automati- cally executes the proper algorithm and controls all the necessary timing to program and verify the operation. writ e verification only detects ?1 s? that are not successfully written to ?0s.? r/b# goes low for the duration of array programming time, t prog. the read status (70h) command and the reset (ffh) command are the only commands valid during the programming operation. bit 6 of the status re gister will reflect the state of r/b#. when the device reaches ready, read bit 0 of the status register to determine if the program operation passed or failed (see figure 19). th e command register st ays in read status register mode until another va lid command is written to it. random data input 85h after the initial data set is input, additional data can be written to a new column address with the random data input (85h) command. the random data input com- mand can be used any number of times in the same page before the page write (10h) command is issued. see figure 20 for the proper command sequence. figure 19: program and read status operation figure 20: random data input i/ox 80h address (5 cycles) 10h 70h r/b# t prog status i/o 0 = 0 program successful i/o 0 = 1 program error d in i/ox 80h address (5 cycles) 85h address (2 cycles) 10h 70h r/b# t prog d in d in status pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 28 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions program page cache mode 80h-15h cache programming is actually a buffered programming mode of the standard pro- gram page command. programming is started by loading the serial data input (80h) command to the command register, followed by five address cycles and a full or partial page of data. the data is initially copied into the cache register, and the cache write (15h) command is then latched to th e command register. data is transferred from the cache register to the data register on the rising edge of we#. r/b# goes low during this transfer time. after the data has been copied into the data register and r/b# returns to high, memory array programming begins. when r/b# returns to high, new data can be written to the cache register by issuing another cache program command sequence. th e time that r/b# stays low will be controlled by the actual programming time. the first time through equals the time it takes to transfer the cache register contents to the data register. on the second and sub- sequent programming passes, transfer from the ca che register to the data register is held off until current data register content has been programmed into the array. bit 6 (cache r/b#) of the status register ca n be read by issuing the read status (70h) command to determine when the cache register is ready to accept new data. the r/b# pin always follows bit 6. bit 5 (r/b#) of the status register can be polled to determine when the actual program- ming of the array is complete for the current programming cycle. if just the r/b# pin is used to determine programming completion, the last page of the program sequence must use the program page (10h) command instead of the cache program (15h) command. if the cache program (15h) command is used every time, including the last page of the programming sequence, status register bit 5 must be used to determine when prog ramming is complete (see figure 21). bit 0 of the status register returns the pass/f ail for the previous page when bit 6 of the status register is a ?1? (ready state). the pass/fail status of the current program opera- tion is returned with bit 0 of the status regist er when bit 5 of the status register is a ?1? (ready state) (see figure 21). figure 21: program page cache mode example notes: 1. see note 3, table 22 on page 43. 2. check i/o[6:5] for inte rnal ready/busy. check i/o[1:0] for pass fail. re# can stay low or pulse multiple times after a 70h command. t cbsy address/ data input 80h 15h address/ data input 80h 15h address/ data input 80h 15h address/ data input 80h 10h t lprog 1 address/ data input 80h 15h address/ data input 80h 10h status output 2 70h t lprog 1 status output 2 70h a: without status reads b: with status reads t cbsy t cbsy t cbsy r/b# i/ox r/b# i/ox pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 29 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions internal data move an internal data move requires two comm and sequences. issue a read for internal data move (00h-35h) command first, then the program for internal data move (85h-10h) command. data moves are only supported within the die from which data is read. read for internal data move 00h-35h the read for internal data move (00h-35h)command is used in conjunction with the program for internal data move (85h-10h) command. first, 00h is written to the command register, then the internal source address is written (5 cycles). after the address is input, the read for internal data move (35h) command writes to the command register. this transfers a page from memory into the cache register. the written column addresses are ignored even though all 5 address cycles are required. the memory device is now ready to accept the program for internal data move command. refer to the command description in the following section for details. program for internal data move 85h-10h after the read for internal data move (00h-35h) command has been issued and r/b# goes high, the program for internal data move (85h-10h) command can be written to the command register. this command transfers the data from the cache register to the data register, and programming of th e new destination page begins. the sequence 85h, destination address (5 cycles), then 10h, is written to the device. after 10h is written, r/b# goes low while the control logic automatically programs the new page. the read status command can be used instead of the r/b# line to determine when the write is complete. when status register bit 6 = ?1,? bi t 0 indicates if the operation was successful. the random data input (85h) command can be used during the program for internal data move command sequence to modify a word or multiple words of the original data. first, data is copied into the cache register using the 00h-35h command sequence, then the random data input (8 5h) command is written along with the address of the data to be modified next. new da ta is input on the external data pins. this copies the new data into the cache register. when 10h is written to the command register, the original data plus the modified data are transferred to the data register, and programming of the new page is started. the random data input command can be issued as many times as necessary before the programming sequence is started with 10h (see figures 22 and 23 on page 30). because internal data move operations do not use external memory, ecc cannot be used to check for errors before programming the data to a new page. this can lead to a data error if the source page contains a bit error due to charge loss or charge gain. in the case that multiple internal data mo ve operations are performed, these bit errors may accumulate without correction. for this reason, it is highly recommended that systems using internal data move operations also use a robust ecc scheme that can correct 2 or more bits per sector. pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 30 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions figure 22: internal data move figure 23: internal data move with random data input i/ox 00h address (5 cycles) 35h 85h address (5 cycles) 10h 70h r/b# t prog t r status i/ox 00h address (5 cycles) 35h 85h address (5 cycles) data data 85h address (2 cycles) unlimited number of repetitions 10h 70h status r/b# t prog t r pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 31 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions block erase operation block erase 60h-d0h erasing occurs at the block level. for ex ample, the mt29f2g08xxc device has 2,048 erase blocks organized into 64 pages per bl ock, 2,112 bytes per page (2,048 + 64 bytes). each block is 132k bytes (1 28k + 4k bytes). the block erase command operates on one block at a time (see figure 24). three cycles of addresses ba[17:6] and pa[5:0] are required. although page addresses pa[5:0] are loaded, they are ?don?t care? and are ignored for block erase operations. see table 4 on page 12 for addressing details. the actual command sequence is a two-st ep process. the erase setup (60h) com- mand is first written to the command register. then three cycles of addresses are written to the device. next, the erase confirm (d0h) command is written to the command register. at the rising edge of we#, r/b# goes low and the control logic automatically controls the timing and erase-verify op erations. r/b# stays low for the entire t bers erase time. the read status (70h) command can be used to check the status of the block erase operation. when bit 6 = ?1,? the erase operation is complete. bit 0 indicates a pass/fail condition where ?0? = pass (see figure 24, and table 11 on page 26). figure 24: block erase operation re# ce# ale cle i/ox 60h address input (3 cycles) status d0h 70h r/b# we# t bers don?t care i/o 0 = 0 erase successful i/o 0 = 1 erase error pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 32 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions one-time programmable (otp) area this micron nand flash device offers a protected, one-time programmable nand flash memory area. ten full pages (2,112 bytes or 1,056 words per page) of otp data is available on the device, and the entire range is guaranteed to be good from the factory. the otp area is accessible only through the otp commands. customers can use the otp area any way they desire; typical uses include programming serial numbers or other data for permanent storage. in micron nand flash devices, the otp area leaves the factory in a non-written state (all bits are ?1s?). programming or partia l-page programming enables the user to pro- gram only ?0? bits in the otp area. the otp area cannot be erased, even if it is not pro- tected. protecting the otp area simply prevents further programming of the otp area. while the otp area is referred to as ?one-time programmable,? micron provides a unique way to program and verify data?bef ore permanently protecting it and prevent- ing future changes. otp programming and protection are accompli shed in two discrete operations. first, using the otp data program (a0h-10h) command, an otp page is programmed entirely in one operation, or in up to four partial-page programming sequences. second, the otp area is permanently protected from further programming using the otp data protect (a5h-10h) command. the pages within the otp area can always be read using the otp data read (afh-30h) command, whether or not it is protected. otp data program a0h-10h the otp data program (a0h-10h) command is used to write data to the pages within the otp area. an entire page can be programmed at one time, or the page can be par- tially programmed up to four times. ther e is no erase operation for the otp pages. the otp data program enables programming into an offset of an otp page, using the two bytes of column address (ca[11:0]). the command is not compatible with the random data input (85h) command. the otp data program command will not execute if the otp area has been protected. to use the otp data program command, issue the a0h command. then issue 5 address cycles: the first 2 address cycles are the column address, and for the remaining 3 cycles, select a page in the range of 02h-00h-00h through 0bh-00h-00h. next, write the data: from 1 to 2,112 bytes (x8 device), or from 1 to 1,056 words (x16 device). after data input is complete, issue the 10h command. the internal control logic automatically executes the proper programming algorithm and controls the necessary timing for programming and veri fication. program verification only detects ?1s? that are not successfully written to ?0s.? r/b# goes low during the duration of the array programming time ( t prog). the read status (70h) command is the only comma nd valid during the otp data program operation. bit 5 of the status register will refl ect the state of r/b#. if bit 7 is ?0,? the otp area has been protected; othe rwise, it is not protected. when the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see table 11 on page 26). it is possible to program each otp page a maximum of four times. pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 33 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions figure 25: otp data program notes: 1. the otp page must be within the 02h?0bh range. we# ce# ale cle re# r/b# i/ox don?t care otp data written (following "good" status confirmatio n) t wc t wb t prog otp data input command program command read status command 1 up to m bytes serial input x8 device: m = 2,112 bytes x16 device: m = 1,056 words a0h col add 1 col add 2 otp page 1 d in n d in m 00h 10h 70h status pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 34 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions otp data protect a5h-10h the otp data protect (a5h-10h) command is used to protect the data in the otp area. after the data is protected, it cannot be programmed further. when the otp area is protected, the pages within the area are no longer programmable and cannot be unpro- tected. to use the otp data protect command, issue the a5h command. next, issue the fol- lowing 5 address cycles: 00h-00h-01h-00h-00h. finally, issue the 10h command. r/b# goes low while the otp area is being protected. the protect command duration is similar to a normal page programming operation, t prog. the read status (70h) command is the only command valid during the otp data protect operation. bit 5 of the status register will reflect the state of r/b#. when the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see table 11 on page 26). figure 26: otp data protect notes: 1. otp data is protected foll owing ?good? status confirmation. w e# ce# ale cle re# r/b# i/ox don?t care t wc t wb t prog otp data protect command otp data protected 1 program command read status command a5h col 00h col 00h 10h 70h status 01h 00h 00h pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 35 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions otp data read afh-30h the otp data read (afh-30h) command is used to read data from a page within the otp area. an otp page within the otp area is available for reading data whether or not the area is protected. to use the otp data read command, issue the afh command. then issue 5 address cycles: the first 2 address cycles are the column address, and for the remaining 3 cycles select a page in the range of 02h-00h-00h through 0bh-00h-00h. finally, issue the 30h command. r/b# goes low ( t r) while the data is moved from the otp page to the data register. the read status (70h) command and the reset (ffh) command are the only commands valid during the otp data read operation. bi t 5 of the status register will reflect the state of r/b#. for details, refer to table 11 on page 26. normal read operation timings apply to otp read accesses (see figure 27). additional pages within the otp area can be selected by repeating the otp data read command. figure 27: otp data read notes: 1. the otp page must be within the 02h?0bh range. we# ce# ale cle re# r/b# i/ox busy d out n afh 00h 00h 30h don?t care otp page 1 col add 2 col add 1 d out n + 1 d out m t r pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 36 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions reset operation reset ffh the reset command is used to put the memory device into a known condition and to abort a command sequence in progress. read, program, and erase commands can be aborted while the device is in the busy state. the contents of the memory location being programmed or the block being erased are no longer valid. the data may be partiall y erased or programmed, and is invalid. the command register is cleared and is ready for the next command. the data register and cache register contents are invalid. the status register contains the value e0h wh en wp# is high; otherwise, it is written with a 60h value. r/b# goes low for t rst after the reset command is written to the command register (see figure 28 and table 12). figure 28: reset operation table 12: status register contents after reset operation condition status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex wp# high ready 11100000e0h wp# low ready and write protected 0110000060h cle ce# w e# r/b# i/ox t rst t wb ffh reset command pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 37 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory command definitions write protect operation it is possible to enable and disable pr ogram and erase commands using the wp# pin. the following figures illustrate the setup time ( t ww) required from wp# toggling until a program or erase command is latched in to the command register. after command cycle 1 is latched, wp# must not be toggled until the command is complete and the device is ready (status register bit 5 is ?1?). figure 29: erase enable figure 30: erase disable figure 31: program enable t ww 60h d0h we# i/ox wp# r/b# t ww 60h d0h we# i/ox wp# r/b# t ww 80h 10h we# i/ox wp# r/b# pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 38 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory error management figure 32: program disable error management micron nand flash devices are specified to have a minimum of 2,008 (n vb ) valid blocks out of every 2,048 total available blocks. this means the devices may have blocks that are invalid when they are shipped. an invalid block is one that contains 1 or more bad bits. additional bad blocks may develop with use. however, the total number of available blocks will not fall below n vb during the endurance life of the product. although nand flash memory devices may contain bad blocks, they can be used quite reliably in systems that provide bad-block mapping, bad-block replacement, and error correction algorithms. this type of soft ware environment ensures data integrity. internal circuitry isolates ea ch block from other blocks, so the presence of a bad block does not affect the operation of the rest of the flash device. the first block (physical block address 00h) fo r each ce# is guaranteed to be free of defects (up to 1,000 program/erase cycles) wh en shipped from the factory. this pro- vides a reliable location for storing bo ot code and critical boot information. before nand flash devices are shipped from micron, they are erased. the factory iden- tifies invalid blocks before shipping by pr ogramming data other than ffh (x8) or ffffh (x16) into the first spare location (column address 2,048 for x8 devices, or column address 1,024 for x16 devices) of the firs t or second page of each bad block. system software should check the first spare address on the first 2 pages of each block prior to performing any eras e or programming operations on the nand flash device. a bad-block table can then be created, allowing system software to map around these areas. factory testing is performed under worst-case conditions. because blocks marked ?bad? may be marginal, it may not be possible to recover this information if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over th e life of the nand flash device, certain pre- cautions must be taken: always check status after a program, erase, or data move operation. under typical conditions, use a minimu m of 1-bit ecc per 528 bytes of data. use a bad-block replacement algorithm. t ww 80h 10h we# i/ox wp# r/b# pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 39 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory electrical characteristics electrical characteristics stresses greater than those listed under ?absolute maximum ratings? (see table 13) may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any ot her conditions above those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maxi- mum rating conditions for extended periods may affect reliability. v cc power cycling micron nand flash devices are designed to prevent data corruption during power tran- sitions. v cc is internally monitored. when v cc goes below approximately 1.1v (1.8v device), or 2.0v (3v device), program and erase functions are disabled. wp# provides additional hardware protection. wp# should be kept at v il during power cycling. when v cc reaches approximately 1.5v (1.8v device) or 2.5v (3v device), a minimum of 10s should be allowed for the nand flash to in itialize before any commands are executed (see figure 33). figure 33: ac waveforms during power transitions table 13: absolute maximum ratings by device voltage on any pin relative to v ss parameter/condition symbol min max unit voltage input mt29fxgxxxac v in ?0.6 +4.6 v mt29fxgxxxbc ?0.6 +2.4 v v cc supply voltage mt29fxgxxxac v cc ?0.6 +4.6 v mt29fxgxxxbc ?0.6 +2.4 v storage temperature t stg ?65 +150 c short circuit output current, i/os ?5ma table 14: recommended operating conditions parameter/condition symbol min typ max unit operating temperature commercial t a 0?70 o c extended ?40 ? +85 o c v cc supply voltage mt29fxgxxxac v cc 2.7 3.3 3.6 v mt29fxgxxxbc 1.70 1.8 1.95 v ground supply voltage v ss 000v we# r/b# wp# vcc 10s high 3v device: 2.5v 1.8v device: 1.5v 3v device: 2.5v 1.8v device: 1.5v undefined don?t care pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 40 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory electrical characteristics table 15: m29fxgxxxac 3v device dc and operating characteristics parameter conditions symbol min typ max unit sequential read current t rc = 30ns; ce# = v il ; i out = 0ma i cc 1? 15 30ma program current ?i cc 2? 15 30ma erase current ?i cc 3? 15 30ma standby current (ttl) ce# = v ih ; wp# = 0v/v cc i sb 1? ? 1ma standby current (cmos) mt29f2gxxaac ce# = v cc - 0.2v; wp# = 0v/v cc i sb 2? 10 50a mt29f4gxxbac ?20100a mt29f8gxxfac ?40200a input leakage current mt29f2gxxaac v in = 0v to v cc i li ? ? 10 a mt29f4gxxbac ? ? 20 a mt29f8gxxfac ? ? 40 a output leakage current mt29f2gxxaac v out = 0v to v cc i lo ? ? 10 a mt29f4gxxbac ? ? 20 a mt29f8gxxfac ? ? 40 a input high voltage i/o[7:0], i/o[15:0] ce#, cle, ale, we #, re#, wp#, r/b# v ih 0.8 x v cc ?v cc + 0.3 v input low voltage (all inputs) ?v il ?0.3 ? 0.2 x v cc v output high voltage i oh = ?400a v oh 2.4 ? ? v output low voltage i ol = 2.1ma v ol ??0.4v output low current (r/b#) v ol = 0.4v i ol (r/b#) 8 10 ? ma pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 41 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory electrical characteristics notes: 1. invalid blocks are blocks that contain 1 or more bad bits. the device may contain bad blocks upon shipment. additional bad blocks may develop over time; however, the total number of available blocks will not drop below n vb during the endurance life of the device. do not erase or program bloc ks marked invalid by the factory. 2. block 00h (the first block) is guaranteed to be valid and does not require error correction up to 1,000 program/erase cycles. 3. the number of invalid blocks in each 4gb section will not exceed 80. table 16: m29fxgxxxbc 1.8v device dc and operating characteristics parameter conditions symbol min typ max unit sequential read current t rc = 50ns; ce# = v il ; i out = 0ma i cc 1? 8 15ma program current ?i cc 2? 8 15ma erase current ?i cc 3? 8 15ma standby current (ttl) ce# = v ih ; wp# = 0v/v cc i sb 1? ? 1 ma standby current (cmos) mt29f2gxxabc ce# = v cc - 0.2v; wp# = 0v/v cc i sb 2? 10 50a mt29f4gxxbbc ? 20 100 a mt29f8gxxfbc ? 40 200 a input leakage current mt29f2gxxabc v in = 0v to v cc i li ??10a mt29f4gxxbbc ??20a mt29f8gxxfbc ??40a output leakage current mt29f2gxxabc v out = 0v to v cc i lo ??10a mt29f4gxxbbc ??20a mt29f8gxxfbc ??40a input high voltage i/o [7:0], i/o [15:0] ce#, cle, ale, we#, re#, wp#, r/b# v ih 0.8 x v cc ?v cc + 0.3 v input low voltage (all inputs) ?v il ?0.3 ? 0.2 x v cc v output high voltage i oh = ?100a v oh v cc ? 0.1 ? ? v output low voltage i ol = 100a v ol ??0.1v output low current v ol = 0.1v i ol (r/b#) 3 4 ? ma table 17: valid blocks parameter symbol device min max unit notes valid block number n vb mt29f2gxxaxc 2,008 2,048 blocks 1, 2 mt29f4gxxbxc 4,016 4,096 mt29f8gxxfxc 8,032 8,192 3 pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 42 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory electrical characteristics notes: 1. these parameters are verified in device characterization and are not 100 percent tested. 2. test conditions: t c = 25c; f = 1 mhz; v in = 0v. notes: 1. verified in device charac terization; not 100 percent tested. notes: 1. timing for t adl begins in the address cy cle, on the final rising edge of we#, and ends with the first rising edge of we# for data input. 2. for page read cache mode and program page cache mode operations, the 3v x16 ac characteristics appl y for 3v x8 devices. 3. for 1.8v devices: during program page cache mode and page read cache mode operations, when v cc = 1.70v, t wc = 55ns min. table 18: capacitance description symbol device max unit notes input capacitance c in mt29f2gxxaxc 10 pf 1, 2 mt29f4gxxbxc 20 mt29f8gxxfxc 40 input/output capacitance (i/o) c io mt29f2gxxaxc 10 pf 1, 2 mt29f4gxxbxc 20 mt29f8gxxfxc 40 table 19: test conditions parameter value notes input pulse le vels mt29fxgxxxac 0.0v to v cc (2.7v?3.6v) mt29fxgxxxbc 0.0v to v cc (1.70v?1.95v) input rise and fall times 5ns input and output timing levels v cc /2 output load mt29fxgxxxac (v cc = 3.0v 10%) 1 ttl gate and cl = 50pf 1 mt29fxgxxxac (v cc = 3.3v 10%) 1 ttl gate and cl = 100pf 1 mt29fxgxxxbc (v cc = 1.70?1.95v) 1 ttl gate and cl = 30pf 1 table 20: ac characteristics: command, data, and address input parameter symbol 3v x16 and 1.8v 3v x8 unit notes min max min max ale to data start t adl 100 ? 100 ? ns 1 ale hold time t alh 10 ? 5 ? ns 2 ale setup time t als 25 ? 10 ? ns 2 ce# hold time t ch 10 ? 5 ? ns 2 cle hold time t clh 10 ? 5 ? ns 2 cle setup time t cls 25 ? 10 ? ns 2 ce# setup time t cs 35 ? 15 ? ns 2 data hold time t dh 10 ? 5 ? ns 2 data setup time t ds 20 ? 10 ? ns 2 write cycle time t wc 45 ? 30 ? ns 2, 3 we# pulse width high t wh 15 ? 10 ? ns 2 we# pulse width t wp 25 ? 15 ? ns 2 wp# setup time t ww 30 ? 30 ? ns pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 43 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory electrical characteristics notes: 1. for page read cache mode and program page cache mode operations, the 3v x16 ac characteristics ap ply for 3v x8 devices. 2. transition is measured 200mv from steady- state voltage with load. this parameter is sampled and not 100 percent tested. 3. if reset (ffh) command is loaded at ready state, the device goes busy for maximum 5s. 4. do not issue a ne w command during t wb, even if r/b# is ready. notes: 1. eight cycles total to the same page. 2. t cbsy max time depends on timi ng between internal progra m completion and data in. 3. t lprog = t prog (last page) + t prog (last - 1 page) - comman d load time (last page) - address load time (last page) ? data load time (last page). table 21: ac characteristics: normal operation parameter symbol 3v x16 and 1.8v 3v x8 unit notes min max min max ale to re# delay t ar 10 ? 10 ns ce# access time t cea ?45?23ns1 ce# high to output high-z t chz ?45?20ns2 cle to re# delay t clr 10 ? 10 ? ns cache busy in page read cache mode (first 31h) t dcbsyr1 ?3?3s cache busy in page read cache mode (next 31h and 3fh) t dcbsyr2 t dcbsyr1 25 t dcbsyr1 25 s output high-z to re# low t ir 0?0?ns1 data output hold time t oh 15 ? 15 ? ns data transfer from nand flash array to data register t r ?25?25s read cycle time t rc 50 ? 30 ? ns 1 re# access time t rea ?30?18ns1 re# high hold time t reh 15 ? 10 ? ns 1 re# high to output high-z t rhz ?30?30ns2 re# pulse width t rp 25 ? 15 ? ns 1 ready to re# low t rr 20 ? 20 ? ns reset time (read/program/erase) t rst ? 5/10/500 ? 5/10/500 s 3 we# high to busy t wb ? 150 ? 150 ns 3, 4 we# high to re# low t whr 80 ? 60 ? ns table 22: program/erase characteristics parameter symbol description typ max unit notes nop number of partial page programs ?8cycles1 t bers block erase time 23ms t cbsy busy time for cache program 3 700 s 2 t lprog last page program time ???3 t prog page program time 300 700 s pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 44 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams timing diagrams figure 34: command latch cycle note: x16: i/o[15:8] must be set to ?0.? figure 35: address latch cycle note: x16: i/o [15:8] must be set to ?0.? we# ce# ale cle i/ox command t wp t ch t cs t alh t dh t ds t als t clh t cls don?t care t alh we# ce# ale cle i/ox col add 1 t wp t wh t cs t dh t ds t als t cls col add 2 row add 1 row add 2 row add 3 don?t care undefined t wc pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 45 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 36: input data latch cycle notes: 1. d in final = 2,111 (x8) or 1,055 (x16). figure 37: serial access cycle after read w e# ce# ale cle i/ox t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in 1 d in final 1 don?t care t wc d in 0 ce# re# i/ox t reh t rp t rr t rc t cea t rea t rea t rea don?t care t rhz t chz t rhz t oh r/b# t oh d out d out d out pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 46 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 38: read status cycle figure 39: page read operation re# ce# we# cle i/ox t rhz t wp t whr t clr t ch t cls t cs t clh t dh t oh t rp t chz t ds t rea t oh t ir 70h status output don?t care t cea d out n d out n + 1 d out m we# ce# ale cle re# r/b# i/ox t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz don?t care col add 1 col add 2 row add 1 row add 2 row add 3 pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 47 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 40: page read operation with ce# ?don?t care? figure 41: random data read operation re# ce# t rea t cea re# ce# ale cle i/ox i/ox out r/b# we# data output t r don?t care address (5 ccycles) 00h 30h we# ce# ale cle re# r/b# i/ox busy col add 1 col add 2 row add1 row add 2 row add 3 00h t r t wb t ar t rr don?t care t rc d out m d out m + 1 col add 1 col add 2 05h e0h t rea t clr d out n d out n + 1 30h t whr column address n column address m pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 48 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 42: page read cache mode operation, part 1 of 2 t wc we# ce# ale cle re# r/b# i/ox column address 0 1 d out t cea t ds t clh t cls t cs t ch t dh don?t care undefined t rr t wb t wb t wb t r column address 0 continued to 1 of next page t rc t rea 30h d out 0 d out 0 d out 1 31h 31h col add 1 col add 2 row add 1 row add 2 row add 3 00h page address m page address m column address 00h page address m + 1 t dcbsyr1 t dcbsyr2 pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 49 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 43: page read cache mode operation, part 2 of 2 cle ce# we# ale re# i/ox r/b# 1 page address m + 1 don?t care undefined page address m + 2 column address 0 continued from 1 of previous page page address m + x column address 0 t clh t ch t rea t cea t ds t dh t rr t wb t wb column address 0 d out 1 d out 0 d out 1 d out 0 d out 1 t cls t cs t rc t dcbsyr2 d out 0 31h t wb 31h 3fh t dcbsyr2 t dcbsyr2 pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 50 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 44: page read cache mode operation without r/b#, part 1 of 2 t wc we# ce# ale cle re# i/ox 30h 70h status d out 0 column address 0 1 d out 0 d out 1 d out column address 00h page address m page address m t cea t ds t clh t cls t cs t ch t dh don?t care 31h 31h column address 0 70h status i/o 6 = 0, cache busy = 1, cache ready i/o 5 = 0, busy = 1, ready continued to 1 of next page col add 1 col add 2 row add 1 row add 2 row add 3 00h 00h 00h t rc t rea 70h status i/o 6 = 0, cache busy = 1, cache ready page address m + 1 pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 51 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 45: page read cache mode operation without r/b#, part 2 of 2 w e# ce# ale cle re# i/ox 1 page address m + 1 don?t care page address m + 2 column address 0 continued from 1 of previous page page address m + x column address 0 t rea t cea t ds t dh column address 0 d out 0 d out 1 d out 31h d out 0 d out 3fh d out 1 d out d out 1 d out 0 t rc d out 31h 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 00h 00h 00h t clh t ch t cls t cs pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 52 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 46: read id operation note: see table 10 on page 25 for byte definitions. figure 47: program page operation we# ce# ale cle re# i/ox address, 1 ccycle 90h 00h byte 2 byte 0 byte 1 byte 3 t ar t rea t whr we# ce# ale cle re# r/b# i/ox t wc t adl serial data input command x8 device: m = 2,112 byte x16 device: m = 1,056 byte program command read status command 1 up to m bytes serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in m 70h status 10h t prog t wb don?t care pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 53 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 48: program page operation with ce# ?don?t care? figure 49: program page operation with random data input cle ce# we# ale i/ox address (5 cycles) data input 10h we# ce# t wp t ch t cs don?t care data input 80h we# ce# ale cle re# r/b# i/ox t wc serial data input command serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in n+1 t adl t adl random data input command column address program command read status command serial input 85h t prog t wb don?t care col add 1 col add 2 d in n d in n+1 70h status 10h pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 54 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 50: internal data move operation figure 51: program page cache mode operation we# ce# ale cle re# r/b# i/ox t wb t prog t wb busy busy t wc internal data move don?t care t adl t whr col add 2 row add 1 row add 2 70h 10h status data n row add 3 col add 1 00h 35h col add 2 row add 1 row add 2 row add 3 col add 1 85h data 1 t r read status command we# ce# ale cle re# r/b# i/ox 15h t cbsy t wb t wb t whr t lprog col add 1 80h 10h 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page - 1 last page serial input program program t wc don?t care 80h t adl row add 3 serial data input pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 55 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 52: program page cache mode operation ending on 15h we# ce# ale cle re# i/ox 15h col add 1 80h 15h 70h status 70h status 70h status col add 2 row add 2 row add 1 row add 3 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page last page ? 1 serial input program program t wc don?t care 80h poll status until: i/o6 = 1, ready to verify successful completion of the last 2 pages: i/o5 = 1, ready i/o0 = 0, last page program successful i/o1 = 0, last page ? 1 program successful t adl t whr t whr t adl serial data input pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 56 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory timing diagrams figure 53: block erase operation notes: 1. see table 10 on page 25 for actual values. figure 54: reset operation we# ce# ale cle re# r/b# i/ox auto block erase setup command erase command read status command busy row address 60h row add 1 row add 2 row add 3 70h status d0h t wc t bers t wb t whr don?t care i/o0 = 0, pass i/o0 = 1, fail cle ce# w e# r/b# i/ox t rst t wb ffh reset command ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 2gb, 4gb, 8gb: x8, x16 nand flash memory package dimensions pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 57 ?2005 micron technology, inc. all rights reserved. package dimensions figure 55: tsop type i note: all dimensions are in millimeters. 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 for reference only 0.50 typ for reference only 12.00 0.08 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. pdf: 09005aef814b01a2 / source: 09005aef814b01c7 micron technology, inc., reserves the right to change products or specifications without notice. 2_4_8gb_nand_m49a__2.fm - rev. d 12/06 en 58 ?2005 micron technology, inc. all rights reserved. 2gb, 4gb, 8gb: x8, x16 nand flash memory revision history revision history rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/06 table 21 on page 43: updated 3v x16 and 1.8v t chz max value to 45ns. rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/06 removed references to power-on auto read (pre) feature. updated web links. ?pin assignments and descriptions? on page 7: added heading. table 1 on page 8: changed table title. table 3 on page 11: in note 2, changed bytes to words. ?read id 90h? on page 24: revised description. figure 25 on page 33: revised otp page. table 16 on page 41: changed part numbers under standby current (cmos), input leakage current, and output leakage current to reflect 1.8v. ?error management? on page 38: revised second bullet. table 21 on page 43: changed t wb (max) from 100ns to 150ns. figure 42 on page 48 and figure 43 on page 49: added t wb timings with r/b# unde- fined. figure 55 on page 57: updated package diagram with 7/18/06 version. rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/06 table 21 on page 43: updated the t whr minimum value from 60ns to 80ns for 3v x16 and 1.8v devices. rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/06 initial release. |
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